Cleanroom Projects and People (Sample)

Project Title: Texas Instruments

Revision Date: 3/1/2009

Entry Date: 7/1/2003

          Startup Date: 2005

          Expansion Date:  

          Country: TX

          City: Dallas / Richardson

          Size: 220,000 sq. ft. ISO Class 5 turbulent cleanroom

          Product: wafers

          Address:  

          Telephone:  

          SIC Description: Semiconductor

          Description: 
          Texas Instruments plans to build a $3 billion wafer fab near the University of Texas at Dallas (UTD). The proposed fab will employ 1,000 workers. It would be built on a TI-owned plot of 90 acres near UTD in Richardson. No other details were given at this time but it is expected that the plant will produce sub-micron, 300-mm wafers. The company has already been processing 300-mm wafers at its DMOS 6 fab in Dallas since 2001. As a result of the chipmaker's decision to build the fab in Texas, the Erik Jonsson School of Engineering and Computer Science at UT Dallas will receive more than $300 million in funds from private and public sources. **As of January 2005, Texas Instruments has broken ground for the 300-mm wafer manufacturing facility. The focus on the new fab will be 65-nm production. The fab is being built on 92.4-acre greenfield site and will feature a more than 220,000 sq. ft. ISO Class 5 turbulent cleanroom. The New Fab One will also include a 300,000 sq. ft. administration building, a 171,000 sq. ft. support wing, and a 166,000 sq. ft. mechanical wing. The fab will produce digital signal processing and analog-based system-on-chip devices for wireless broadband and digital consumer applications. TI plans to construct the building and infrastructure ahead of market demands, followed by stages of equipment installation as demand increases. Environmental features include water recycling for manufacturing, waste heat recovery, natural day lighting, and solar water heating. **As of March 2005, TI is delivering pre-production samples of cell-phone baseband chips made in its new 65-nm CMOS process technology. Fully qualified production is expected towards the end of 2005. The 65-nm process and design shrink the siicon area by half compared to 90-nm parts. TI has also applied strained-silicon techniques to boost transistor performance by 40% and reduce leakage power from idle transistors by a factor of 1000. These processes give TI the ability to pack hundreds of millions of transistors that support both analog and digital functionality in tight integrated system-on-a-chip solutions. TI's 65-nm process is planned for both 200mm and 300-mm production.